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Flip-Flops & Counters
ECE
Digital Logic Design
Simulation
Learn
Assessment
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Timing diagram
0 edges
Press
Clock ▸
to start the trace
Flip-flop
0
J
0
K
CLK
JK
0
Q
1
Q̄
The universal flip-flop. J=K=1 toggles — no forbidden state.
Flip-flop type
SR
D
JK
T
Inputs & clock
J
0
K
0
Q
0
Q̄
1
Clock ▸
Free run
Clear trace
State
Q
0
Q̄
1
J
K
Q next
0
0
0
0
1
0
1
0
1
1
1
1